Ioriveur’s Simple Serial Transmitter in Verilog

This is the Verilog source code.
How it works is explained here.

module transmittr (
input Srialclk,
input Wrtcmplt,
input [11:0]data,
output SrialData
reg [11:0]Datareg;
reg Endflg;
wire Endtoken;
assign Endtoken = Endflg & ~Srialclk;
assign SrialData = Endtoken ? ~Datareg[0] : Datareg[0];
reg [3:0]ShftCount = 0;
always@( posedge Srialclk )begin
Datareg[11:0] <= { 1'b0, Datareg[11:1] };
ShftCount <= ShftCount + 4'h1;
if ( ShftCount == 4'hB )begin
Endflg <= 1'b1;
if( Wrtcmplt )begin
ShftCount <= 0;
else if ( ShftCount == 4'h0 )begin
Endflg <= 0;
Datareg[11:0] <= data[11:0];


Main actor

Serial Clock(input)   —  it is from master receiver.

Serial Data(output)  —  it is LSB of shift register.

Shift Register            —  it is register. In this case, it has 12 bit width.

Parallel Data in         —  it is wide parallel data. It has same width as Register.

End flag                      — it goes H when it send last bit.

Basic operation

When serial clk rise up, the shift register may be right shifted, if the data is not empty.
In case it is empty, data are loaded in shift register.

The output is LSB of shift register, so data will be sent out from LSB to MSB.

Why can I know register is empty or not ?

See the code. Just counting.

How Can I notice the Last bit is Last bit ?

When the rising down edge of the cycle it send last bit, the serial out is reverse.

Never expect this the serial out is change at rising down edge of serial clk.

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